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https://github.com/scopatz/nanorc
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1
nanorc
1
nanorc
@ -73,6 +73,7 @@ include "~/.nano/systemd.nanorc"
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include "~/.nano/tcl.nanorc"
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include "~/.nano/tcl.nanorc"
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include "~/.nano/tex.nanorc"
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include "~/.nano/tex.nanorc"
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include "~/.nano/vala.nanorc"
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include "~/.nano/vala.nanorc"
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include "~/.nano/verilog.nanorc"
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include "~/.nano/vi.nanorc"
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include "~/.nano/vi.nanorc"
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include "~/.nano/xml.nanorc"
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include "~/.nano/xml.nanorc"
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include "~/.nano/xresources.nanorc"
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include "~/.nano/xresources.nanorc"
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84
verilog.nanorc
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84
verilog.nanorc
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@ -0,0 +1,84 @@
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## (System)Verilog syntax highlighting.
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# See http://savannah.gnu.org/patch/?9356
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# From bc2635d9c8dcf6a71e834582501546fac6bdbfff Mon Sep 17 00:00:00 2001
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# From: Ben Rosser <rosser.bjr@gmail.com>
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# Date: Tue, 23 May 2017 17:43:15 -0400
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# Subject: [PATCH] Add Verilog nanorc file for syntax highlighting
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# This adds a verilog.nanorc file for syntax highlighting of Verilog
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# and SystemVerilog code. It is based off of the nanorc files for
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# Python and C.
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# All keywords in both Verilog (*.v, *.vh) and SystemVerilog (*.sv,
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# *.svh) are listed. Compiler directives (commands beginning with a
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# backtick) and builtin functions are also colorized.
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# Possibly the color scheme could use some work, but this is at least
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# a starting point. I based verilog.nanorc off of c.nanorc and
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# python.nanorc.
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syntax "verilog" "\.(v|vh|sv|svh)$"
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# I don't think we want this.
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#color brightred "\<[A-Z_][0-9A-Z_]+\>"
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# Module, package, etc. definitions: colorize their names.
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# (I'm not sure if brightred is a good color).
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icolor brightred "(module|package|task|interface|program|class) [0-9A-Z_]+"
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icolor brightred "function [0-9A-Z_]+ [0-9A-Z_]+"
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# Verilog keywords, taken from http://svref.renerta.com/sv00003.htm.
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color green "\<(always|and|assign|automatic|begin|buf|bufif0|bufif1|case|casex|casez|cell|class|cmos|config)\>"
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color green "\<(deassign|default|defparam|design|disable|edge|else|end|endcase|endconfig|endfunction|endgenerate)\>"
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color green "\<(endmodule|endprimitive|endspecify|endtable|endtask|event|for|force|forever|fork|function|generate)\>"
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color green "\<(genvar|highz0|highz1|if|iff|ifnone|incdir|include|initial|inout|input|instance|integer|join)\>"
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color green "\<(large|liblist|library|localparam|macromodule|medium|module|nand|negedge|nmos|nor|noshowcancelled)\>"
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color green "\<(not|notif0|notif1|null|or|output|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup)\>"
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color green "\<(pulsestyle_onevent|pulsestyle_ondetect|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran)\>"
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color green "\<(rtranif0|rtranif1|scalared|showcancelled|signed|small|specify|specparam|strong0|strong1|supply0)\>"
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color green "\<(supply1|table|task|time|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|unsigned|use|uwire)\>"
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color green "\<(vectored|wait|wand|weak0|weak1|while|wire|wor|xnor|xor)\>"
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# System Verilog keywords, taken from same source.
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color green "\<(alias|always_comb|always_ff|always_latch|assert|assume|before|bind|bins|binsof|bit|break|byte)\>"
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color green "\<(chandle|clocking|const|constraint|context|continue|cover|covergroup|coverpoint|cross|dist|do)\>"
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color green "\<(endclass|endclocking|endgroup|endinterface|endpackage|endprogram|endproperty|endsequence|enum)\>"
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color green "\<(expect|export|extends|extern|final|first_match|foreach|forkjoin|ignore_bins|illegal_bins|import)\>"
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color green "\<(inside|int|interface|intersect|join_any|join_none|local|logic|longint|matches|modport|new|package)\>"
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color green "\<(packed|priority|program|property|protected|pure|rand|randc|randcase|randsequence|ref|return)\>"
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color green "\<(sequence|shortint|shortreal|solve|static|string|struct|super|tagged|this|throughout|timeprecision)\>"
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color green "\<(timeunit|type|typedef|union|unique|var|virtual|void|wait_order|wildcard|with|within)\>"
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# We need to go through these and decide if everything should be the same color, and remove extra things from C.
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# I don't think this is wanted.
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#color green "\<((s?size)|((u_?)?int(8|16|32|64|ptr)))_t\>"
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# Builtin function names (e.g. $display).
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icolor cyan "\$[0-9A-Z_]+"
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# Macros. Here are some of the standard ones, as per http://verilog.renerta.com/source/vrg00008.htm.
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#color cyan "^[[:space:]]*`[[:space:]]*(define|include(_next)?|timescale|(un|ifn?)def|endif|el(sif|se)|if|resetall)"
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#color cyan "^[[:space:]]*`[[:space:]]*(celldefine|endcelldefine|default_nettype|unconnected_drive|nounconnected_drive)"
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# This isn't complete and it may be better to just colorize `(string), like so:
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icolor cyan "^[[:space:]]*`[0-9A-Z_]+"
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# I'm not sure what this line does... it was in c.nanorc.
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#color brightmagenta "'([^'\]|(\\["'abfnrtv\\]))'" "'\\(([0-3]?[0-7]{1,2}))'" "'\\x[0-9A-Fa-f]{1,2}'"
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# Strings. In general you will want your strings and comments to come last,
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# because highlighting rules are applied in the order they are read in.
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color brightyellow ""([^"]|\\")*"" "<[^[:blank:]=]*>"
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# Multiline strings. This regex is VERY resource intensive,
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# and sometimes colours things that shouldn't be coloured.
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###color brightyellow start=""(\\.|[^"])*\\[[:space:]]*$" end="^(\\.|[^"])*""
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# Comments.
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color brightblue "//.*"
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color brightblue start="/\*" end="\*/"
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# Reminders.
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color ,yellow "\<(FIXME|TODO|XXX)\>"
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# Trailing whitespace.
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color ,green "[[:space:]]+$"
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@ -1,5 +1,5 @@
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syntax "yaml" "\.ya?ml$"
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syntax "yaml" "\.ya?ml$"
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comment "#"
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#comment "#"
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header "^---" "%YAML"
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header "^---" "%YAML"
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# Values
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# Values
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